PS=PS_0, COL=COL_0, ADVH=ADVH_0, AM=AM_0, ADVP=ADVP_0, BL=BL_0, SYNCEN=SYNCEN_0
SRAM control register 0
| PS | Port Size 0 (PS_0): 8bit 1 (PS_1): 16bit |
| SYNCEN | Select SRAM controller mode. 0 (SYNCEN_0): Asynchronous mode is enabled. 1 (SYNCEN_1): Synchronous mode is enabled. |
| BL | Burst Length 0 (BL_0): 1 1 (BL_1): 2 2 (BL_2): 4 3 (BL_3): 8 4 (BL_4): 16 5 (BL_5): 32 6 (BL_6): 64 7 (BL_7): 64 |
| AM | Address Mode 0 (AM_0): Address/Data MUX mode 1 (AM_1): Advanced Address/Data MUX mode 2 (AM_2): Address/Data non-MUX mode 3 (AM_3): Address/Data non-MUX mode |
| ADVP | ADV# polarity 0 (ADVP_0): ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. 1 (ADVP_1): ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. |
| ADVH | ADV# level control during address hold state 0 (ADVH_0): ADV# is high during address hold state. 1 (ADVH_1): ADV# is low during address hold state. |
| COL | Column Address bit width 0 (COL_0): 12 Bits 1 (COL_1): 11 Bits 2 (COL_2): 10 Bits 3 (COL_3): 9 Bits 4 (COL_4): 8 Bits 5 (COL_5): 7 Bits 6 (COL_6): 6 Bits 7 (COL_7): 5 Bits 8 (COL_8): 4 Bits 9 (COL_9): 3 Bits 10 (COL_10): 2 Bits 11 (COL_11): 12 Bits 12 (COL_12): 12 Bits 13 (COL_13): 12 Bits 14 (COL_14): 12 Bits 15 (COL_15): 12 Bits |